Electronic Test and Measurement White Papers

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By: Dell     Published Date: Nov 15, 2016

Make your employees happier, increase their performance and reduce IT support costs by upgrading to a Latitude 5470. Dell partnered with Principled Technologies to create three productivity-based workflows to see how quickly the new Dell Latitude E5470 laptop powered by the latest 6th generation Intel® Core™ i5-6300U processor performed compared to previous generations. • Starting computer and programs is 33% faster • Opening/using several applications at one time is 29% faster • Preparing a video is 18% faster How do these substantial performance improvements pay for themselves and make your employees happier? Read on.

Tags : windows, processors, laptop, system information, intel core, project management, electronic test and measurement
    
By: Mentor Graphics     Published Date: Apr 25, 2016

Over the years, two major approaches to SERDES simulation have emerged and gained popularity: time-domain (or bit-by-bit) and statistical. Both are used to build the eye diagram and bit-error ratio (BER), and each has its benefits and limitations.

Tags : mentor graphics, analysis flow, bit by bit, serdes, ber, gigabit networking, internetworking hardware, electronic test and measurement, embedded systems and networking
    
By: Mentor Graphics     Published Date: Oct 08, 2014

This paper reports on common layout requirements related to SERDES designs, and how HyperLynx DRC can help identify issues on PCB boards that violate these requirements.

Tags : mentor graphics, boards, serdes, pcb boards, drc, gigabit networking, internetworking hardware, best practices, electronic design automation, electronic test and measurement, power and cooling
    
By: Collaborative Consulting     Published Date: Dec 20, 2013

Enabling business value through the Mobile Web requires new thinking as well as a shift in technology. Putting “mobile first” and implementing services-based architectures are among the critical steps. The options are limited only to the imaginations of the designers but must be driven by the user’s context.

Tags : collaborative consulting, business value, user expectations, mobile web, service architecture, technology challenges, information technology, program management, software solutions, context and services, wireless, business activity monitoring, electronic test and measurement
    
By: Mentor Graphics     Published Date: Sep 01, 2010

This paper will examine current methods used to eliminate waived errors at the chip level and describe a new automatable method for identifying and removing waived errors from DRC results.

Tags : mentor graphics, automated drc, violation waiver management, ip block integration, design rule checking, tcp/ip protocol, application integration, business process automation, electronic design automation, system on a chip, electronic test and measurement, integrated circuits and semiconductors, data center design and management
    
By: Mentor Graphics     Published Date: Sep 01, 2010

This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use.

Tags : mentor graphics, calibre pattern matching, svrf, verification rules, ic design, electronic design automation, system on a chip, electronic test and measurement, embedded design, electromechanical & mechanical, integrated circuits and semiconductors
    
By: Mentor Graphics     Published Date: Sep 01, 2010

What Is CFA and Why Do I Need It? This five-part paper series examines the conditions that led to the development of recommended rules, and describes the process by which automated design analysis and rule verification can help designers optimize designs to the fullest and most efficient use of area, while still ensuring manufacturability.

Tags : mentor graphics, critical feature analysis, cfa, design for manufacturing, dfm, automated design analysis, rule verification, electronic design automation, system on a chip, electronic test and measurement, embedded design, embedded systems and networking, electromechanical & mechanical, integrated circuits and semiconductors
    
By: Mentor Graphics     Published Date: Sep 01, 2010

This paper will examine the implementation and demonstrate the benefits of eqDRC through a variety of examples comparing traditional DRC with eqDRC approaches.

Tags : mentor graphics, equation-based drc, nanometer design, design rule checks, drceqdrc, electronic design automation, system on a chip, electronic test and measurement, embedded design, embedded systems and networking, electromechanical & mechanical, integrated circuits and semiconductors
    
By: Mentor Graphics     Published Date: Jun 04, 2010

The Mechanical Analysis Division of Mentor Graphics (formerly Flomerics) provides the world's most advanced computational fluid dynamics products. Our simulation software and consultancy services eliminate mistakes, reduce costs, and accelerate and optimize designs involving heat transfer and fluid flow before physical prototypes are built.

Tags : mentor graphics, fluid dynamics simulation, aerospace design, mechanical analysis, cfd, electronic design automation, electronic test and measurement, embedded design, electromechanical & mechanical
    
By: Mentor Graphics     Published Date: Jun 04, 2010

The focus of this paper is a combined electrical, thermal and optical characterization of power LED assemblies. Thermal management play important role in case of power LEDs, necessitating both physical measurements and simulation.

Tags : mentor graphics, electrical, thermal, optical characterization, power led assemblies, junction temperature, electronic test and measurement, boards & modules, embedded systems and networking, electromechanical & mechanical, optoelectonics & displays
    
By: Ramtron     Published Date: Nov 11, 2009

Today's technological innovation demands high performance coupled with low environmental impact. These dual requirements are driving components of the semiconductor industry which informs many global businesses and consumer lives.

Tags : f-ram, bbsram, random access memory, ram, novram, ecopack, electronics, semiconductor, memory, ramtron, system on a chip, electronic test and measurement, embedded design, boards & modules, embedded systems and networking, integrated circuits and semiconductors
    
By: Mentor Graphics     Published Date: Sep 11, 2009

"As the number of enhancements to various Hardware Description Languages (HDLs) has increased over the past year, so too has the complexity of determining which language is best for a particular design. Many designers and organizations are contemplating whether they should switch from one HDL to another. This paper compares the technical characteristics of three, general-purpose HDLs.

Tags : comparison of vhdl, verilog and systemverilog, mentor graphics, hardware description languages (hdls), vhdl (ieee-std 1076), verilog (ieee-std 1364), ieee standard, accellera, analog communications, digital signal processing, electronic design automation, system on a chip, electronic test and measurement, embedded design, boards & modules, embedded systems and networking, electromechanical & mechanical, optoelectonics & displays, packaging and interconnects, passive & discrete components
    
By: TechInsights     Published Date: Sep 01, 2009

Join us at ESC Boston, September 21-24 at the Hynes Convention Center, in Boston, MA. Expo registration is FREE, and advanced registration pricing is still available for conference packages.

Tags : embedded systems, conference, boston, esc boston, build your own embedded system, atom, windows embedded, classes, tutorials, wired, wireless, programmable logic, system integration, debugging, verification, dsp, multimedia programming, design team management, security, multi-core
    
By: Mentor Graphics     Published Date: Apr 03, 2009

A powerful signal integrity analysis tool must be flexibility, easy to use and integrated into an existing EDA framework and design flow. In addition, it is important for the tool to be accurate enough. This report reviews a validation study for the Mentor Graphics HyperLynx 8.0 PI tool to establish confidence in using it for power integrity analysis.

Tags : mentor graphics, pdn simulation, eda framework, mentor hyperlynx 8.0 pi, integrity analysis, virtual prototypes, esr, capacitor, power distribution network, vrm, voltage regulator module, signal, smas, analog models, backward crosstalk, capacitive crosstalk, controlling crosstalk, correct emc problems, correct emi problems, cross talk
    
By: Mentor Graphics     Published Date: Apr 03, 2009

For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.

Tags : mentor graphics, equalized serial data links, design flow, high loss channels, tektronix, pcb, bit error rate, ber, ieee, serdes, simulation, system configuration, mentor graphics hyperlynx, simplified symmetric trapezoidal input, duty cycle distortion, ber contours, electronics, analog models, backward crosstalk, capacitive crosstalk
    
By: Mentor Graphics     Published Date: Apr 03, 2009

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

Tags : power integrity effects, mentor graphics, high density interconnect, hdi, chip pinouts, perforation, multilayer or build-up multilayer, bum, sequential build-up technologies, sbu, buried via holes, bvhs, dielectric materials, photosensitive, laser drilling, plasma drilling, microvia, plated through-holes, pths, power distribution network
    
By: Mentor Graphics     Published Date: Apr 03, 2009

The success of any consumer electronic device depends to a large extent on the appeal of the user interface (UI) and how easy the device is to use. Studies show that good cosmetic design can encourage users to explore the full range of features and often engenders the perception that a product is easier to use. So if the benefits of a great looking, easy-to-use UI are so clear, why are so many products still falling short of customer expectations? The solution lies in taking a fresh new approach a consumer electronic device UI plays. By identifying common UI functionality and implementing it in a reusable and customizable way, we can make it far easier for embedded engineers to deliver visually engaging and easy-to-use consumer electronic products.

Tags : inflexion platform ui, user interface, consumer electronic device, mentor graphics, ui functionality, media player, mobile phone, tv set-top box, inflexion platform ui, pc-based ui designer tool, embedded component, presentation layer, integration api, xml-based ui template, ui perspective, embedded gui, embedded gui design, embedded gui development, embedded gui prototype, embedded ui
    
By: Mentor Graphics     Published Date: Apr 03, 2009

Moving to C++ presents opportunities for higher programmer productivity. The requirements of embedded systems, however, demand that the adoption of C++ be carefully measured for the performance impact of run-time costs present in C++, but not in C. This talk suggests strategies for developers who are starting their acquaintance with C++.

Tags : c++, coding, developer, programming, programmer, mentor graphics, run-time costs, embedded systems, ansi/iso c[, risc, first principle, cost evaluation, declaration, evaluation principle, initialized static consts, arbitrary placement of declarations, overloading, function in-lining, multiple inheritance, run-time type identification
    
By: TDI Transistor Devices     Published Date: Feb 06, 2009

Uninterruptible Power Solutions are often solved at the facility level with unnecessarily large, inefficient, expensive and complex AC UPS systems. While this provides an easy demarcation line between the facility and end equipment, with each focusing on a different part of the problem, it also results in overall operating efficiency and total cost of ownership being difficult to ascertain and optimize.

Tags : tdi, transistor devices, data processing, uninterruptible power solutions, ups, operating efficiency, electronics, analog communications, digital signal processing, electronic design automation, system on a chip, electronic test and measurement, embedded design, power sources & conditioning devices
    
By: TDI Transistor Devices     Published Date: Feb 06, 2009

Modern Electronic Systems are quite often powered from a three-phase power source. While utilizing power modules that operate directly from three-phase power might seem to provide optimal simplicity and flexibility, the added complexity required to realize three-phase power factor corrected circuitry usually negates any potential savings.

Tags : tdi, transistor devices, electronic power systems, single phase power, three phase power, power transfer maximization, component count, three phase circuits, electronics, analog communications, digital signal processing, electronic design automation, system on a chip, electronic test and measurement, embedded design, power sources & conditioning devices
    
By: Intermec     Published Date: Aug 09, 2012

While production is often optimized and automated, producing the necessary documentation often is not. Creating the necessary job tickets, component IDs, and product labels for manufacturing is a growing source of waste and error. This white paper will explain how manufacturers can realize tangible improvements with proper printers and media.

Tags : intermec, manufacturers, printer, optimization, business intelligence, business management, business process management, ip faxing, total cost of ownership, productivity, electronic design automation, electronic test and measurement, electromechanical & mechanical, technology
    
By: Kingston     Published Date: Feb 15, 2011

Learn how to balance the positive and negative effects of memory utilization in virtual infrastructures to better handle system workload and priority--while improving server utilization

Tags : virtualization, memory overcommitment, memory performance, memory reclamation, vmware, memory utilization, consolidation ratios, server memory, server utilization, memory ballooning, vmkernal swapping, capacity planning, vmware esx 4.0, active directory, bandwidth management, convergence, distributed computing, ethernet networking, fibre channel, gigabit networking
    
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